发明名称 Content addressable memory devices determining entry data priority by valid data length
摘要 A content addressable memory device which determines the top priority entry data without assigning priorities to addresses. If ternary data stored in a cell is invalid data, and other cell at the same bit position stores valid data of entry data identical to an entry key, the entry data is determined not to be a candidate of the top priority entry data. The last entry data which has not determined not to be a candidate is determined to be the top priority data. Compared to the conventional technology which relied on the relationship between a memory address and a priority, the performance of memory system is significantly improved.
申请公布号 US6542392(B2) 申请公布日期 2003.04.01
申请号 US20020080559 申请日期 2002.02.25
申请人 FUJITSU LIMITED 发明人 YANAGAWA MIKI
分类号 G11C15/04;(IPC1-7):G11C15/00 主分类号 G11C15/04
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