发明名称 |
Semiconductor integrated circuit device using static memory cells with bit line pre-amplifier and main amplifier |
摘要 |
A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.
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申请公布号 |
US6542424(B2) |
申请公布日期 |
2003.04.01 |
申请号 |
US20020173433 |
申请日期 |
2002.06.18 |
申请人 |
HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
ENDO HITOSHI;WAKASUGI KATSUHIKO;SATO YOUICHI;SATO KAZUYOSHI |
分类号 |
G11C7/06;G11C7/18;G11C11/419;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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