发明名称 |
Method and model for regulating the computational and memory requirements of a compressed bitstream in a video decoder |
摘要 |
An apparatus for the verification of compressed objected-oriented video bitstream includes a set of verifier models: Video Complexity Verifier (VCV), Video memory Verifier (VMV) and Video Presentation Verifier (VPV). The models specify the behavior of a decoder for variable VOP size and rate and define new parameters and bounds to measure and verify the computational and memory resources that the bitstream demands. They can be used in the video encoder or in the verification of pre-compressed video distribution.
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申请公布号 |
US6542549(B1) |
申请公布日期 |
2003.04.01 |
申请号 |
US19990417465 |
申请日期 |
1999.10.12 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
TAN THIOW KENG;HU GUO RONG |
分类号 |
H04N7/24;H04N7/26;(IPC1-7):H04B1/66;G06K9/46;H04N7/12 |
主分类号 |
H04N7/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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