| 发明名称 |
Low voltage planar power MOSFET with serpentine gate pattern |
| 摘要 |
A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.
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| 申请公布号 |
US6541820(B1) |
申请公布日期 |
2003.04.01 |
| 申请号 |
US20000536903 |
申请日期 |
2000.03.28 |
| 申请人 |
INTERNATIONAL RECTIFIER CORPORATION |
发明人 |
BOL IGOR |
| 分类号 |
H01L29/417;H01L29/78;(IPC1-7):H01L29/76 |
主分类号 |
H01L29/417 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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