发明名称 Read port design and method for register array
摘要 A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.
申请公布号 US6542423(B1) 申请公布日期 2003.04.01
申请号 US20010955619 申请日期 2001.09.18
申请人 FUJITSU LIMITED 发明人 KALYANASUNDHARAM VYDHYANATHAN;NAINI AJAY
分类号 G11C7/00;G11C7/10;G11C7/12;G11C8/00;(IPC1-7):G11C7/00 主分类号 G11C7/00
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