发明名称 |
Serializer/deserializer embedded in a programmable device |
摘要 |
In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.
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申请公布号 |
US6542096(B2) |
申请公布日期 |
2003.04.01 |
申请号 |
US20010939533 |
申请日期 |
2001.08.24 |
申请人 |
QUICKLOGIC CORPORATION |
发明人 |
CHAN ANDREW K.;APLAND JAMES M.;GUNARATNA SENANI;MUDUNURI SUNILKUMAR G.;YAP KET-CHONG |
分类号 |
G11C7/10;G11C7/22;H04L7/00;H04L7/033;H04L7/10;(IPC1-7):H03M9/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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