发明名称 ELECTRO MAGNETIC INTERFERENCE REDUCTION PHASE LOCKED LOOP
摘要 PURPOSE: An electro magnetic interference(EMI) reduction phase locked loop(PLL) is provided to reduce the amount of the EMI as well as to relatively reduce the layout area by not employing a read only memory(ROM), and obtain a broadband frequency. CONSTITUTION: An electro magnetic interference(EMI) reduction phase locked loop(PLL) includes a pre-divider(401) for outputting a reference frequency signal divided an input signal by a predetermined value, a phase detector(403) for receiving the reference frequency signal and a predetermined feedback signal, for generating the signal corresponding to the phase difference between the reference frequency signal and the feedback signal and for outputting a control voltage obtained by processing the corresponding signal, a voltage controlled oscillator(VCO)(405) for receiving the control voltage and a plurality of switching control signals, for outputting a first oscillation signal with a predetermined frequency in response to the control voltage and for outputting a second oscillation signal in response to the plurality of switching control signal, a main divider(407) for outputting the feedback signal to indicate the increase and decrease of the frequency of the first oscillation signal by receiving the second oscillation signal, a modulation control block(409) for outputting the plurality of switching control signal by receiving a modulation frequency data, a modulation rate data, the feedback signal and the second oscillation signal and a post divider(411) for outputting the signal divided by a predetermined value by receiving the first oscillation signal.
申请公布号 KR20030026211(A) 申请公布日期 2003.03.31
申请号 KR20020043695 申请日期 2002.07.24
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JUN, PIL JAE;LEE, MYEONG SU
分类号 H03L7/093;(IPC1-7):H03L7/093 主分类号 H03L7/093
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