发明名称
摘要 PURPOSE:To always hold a VICS beacon in a satisfactory operating state by detecting the clock signals of in phase and opposite phase transmitters, and outputting an abnormality signal when one or both clock signals are not detected. CONSTITUTION:The in-phase and opposite phase clock signals are inputted to the inverted input terminal and non-inverted input terminal of a first operating amplifier 1, and the output of the first operating amplifier 1 is the difference of the two signals whose phases deviate by 180 deg., that is, a value obtained by adding the absolute values. When a fault occurs at the transmitters, and one of the AM modulations is not operated, the clock signal of one system is not generated, and the output waveform of the operating amplifier 1 becomes the waveform of the relatively low value inputted to one terminal. Moreover, when the both clock signals are not generated due to the fault of the transmitters, the output of the operating amplifier 1 is turned to 0. When abnormality occurs at the transmitters, and the AM modulation of the two systems is not normally operated, an abnormality detection signal is obtained from an output terminal 7 of the circuit.
申请公布号 JP3392175(B2) 申请公布日期 2003.03.31
申请号 JP19930050916 申请日期 1993.03.11
申请人 发明人
分类号 G01S1/68;G08G1/09;H04B1/04;H04B1/16;H04B7/26;H04L27/32 主分类号 G01S1/68
代理机构 代理人
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