| 摘要 |
PURPOSE: A circuit for generating an internal address of a semiconductor memory device is provided to reduce power consumption in a refresh process by generating an internal refresh address for refreshing only a selected partial array. CONSTITUTION: A binary counter portion is formed with the first to the twelfth binary counters(C11-C22). The twelfth binary counter(C22) generates the most significant internal address signal and a counter output signal. The eleventh binary counter(C21) generates the eleventh internal address signal and a counter output signal. The first to the tenth binary counters(C11-C20) generate internal address signals and counter output signals, respectively. The first to the tenth binary counters(C11-C20) generate the first to the tenth address signals. The first to the tenth binary counters(C11-C20) are used as binary counters for reducing sequentially output signals. A control portion(101) receives the output signals of the twelfth and the eleventh binary counters(C22,C21), the first and the second selection signals, a self refresh signal, and a refresh signal and outputs a control signal for controlling the binary counter portion and the internal address signals of the twelfth and the eleventh binary counters(C22,C21).
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