| 摘要 |
<p>PURPOSE: A duty correction circuit is provided to correct duty of a CMOS clock by using a duty check block for determining duty of a clock signal and a duty correction block. CONSTITUTION: A duty check block(101) is used for receiving clock signals and determining each duty of clock signals. The determined clock signals are used as control signals(duty40%,duty50%,duty60%) for controlling a duty correction block(103). The duty correction block(103) is used for delaying the clock signals and correcting the duty by using the control signals(duty40%,duty50%,duty60%) of the duty check portion(101). A clock buffer portion(105) receives an output signal from the duty correction portion(103) generates a clock signal and a clock bar signal having a phase difference of 180 degrees.</p> |
