发明名称 HARDWARE BOARD AND DEBUG ALGORITHM USED FOR WRITING SYSTEM PROGRAM USING SOC
摘要 PURPOSE: A hardware board and a debug algorithm used for writing a system program using a SOC(System On a Chip) are provided to shorten time for developing an application program operating an SOC product having a metal routing structure that the power is supplied to respective IP(Intellectual Property) blocks from different pins. CONSTITUTION: The hardware board includes a plurality of SOCs(330), a reset control circuit(310) and a peripheral circuit(350). The SOC(330) includes more than two IP blocks, understands respective characteristics of the IP blocks through a J-TAG using a plurality of input/output terminal, is formed by the metal routing in order to make the corresponding block directly receive the power supplied from the outside of a chip through the pins as many as the number of the IP blocks. The reset control circuit(310) controls the power supply of the corresponding pins of the SOC. The peripheral circuit(330) is related to operation and data input/output. The SOC(330), the reset control circuit(310) and the peripheral circuit are controlled by a debug equipment.
申请公布号 KR20030025057(A) 申请公布日期 2003.03.28
申请号 KR20010057980 申请日期 2001.09.19
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHOI, TAE SEONG
分类号 G06F9/24;(IPC1-7):G06F9/24 主分类号 G06F9/24
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