发明名称 |
MEMORY INSPECTING CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To test a memory while suppressing increment of circuit scale. SOLUTION: This circuit has a test signal generating section 14 generating a test signal by combination of signal lines being less than the number of data input lines of a memory 16 to be tested, a path selecting section 15 is set so that a test signal from the test signal generating section 14 is supplied to the memory 16 to be inspected, a plurality of test signals are outputted by path selection of the path selecting section 15 and a plurality of tests are performed with simple constitution.
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申请公布号 |
JP2003092000(A) |
申请公布日期 |
2003.03.28 |
申请号 |
JP20010281410 |
申请日期 |
2001.09.17 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
HASEGAWA YUICHI |
分类号 |
G01R31/28;G11C29/00;G11C29/02;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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