发明名称 METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ELECTRONIC EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit capable of reducing generation of noise and EMS. SOLUTION: Blocks of same type sequential circuits of different set up time and hold time, and the same functions, block size, terminal number, terminal position, and wiring prohibiting information are prepared in advance. Based on simulation after block layout and wiring between blocks, sequential circuits without complying with timing standards are replaced by sequential circuits of different set up time and hold time (step 130). In addition, the sequential circuits disposed are replaced by same type sequential circuit of different set up time and hold time to reduce the number of sequential circuits in which clock signals are changed within a prescribed time (step 140).
申请公布号 JP2003091569(A) 申请公布日期 2003.03.28
申请号 JP20010281830 申请日期 2001.09.17
申请人 NEC CORP 发明人 NAKAJIMA KAZUHIRO
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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