| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve the efficiency and precision of logic synthesis after clock tree synthesis, arrangement and wiring at every hierarchy block, timing analysis and clock synthesis. SOLUTION: A semiconductor circuit is provided with the hierarchy block having a first clock synchronous cell operated on a clock and multiple second clock synchronous cells which operate on the clock similar to the clock and which are not included in the hierarchy block. In the hierarchy block and the multiple second clock synchronous cells, the clock is transmitted through clock wiring. A first clock buffer where clock wiring is made an input is inserted between the clock input terminals of the multiple second clock synchronous cells and clock wiring supplying clock signals to the clock input terminals. Thus, clock wiring is divided into first clock wiring connected to the hierarchy block and second clock wiring connected to the second clock synchronous cell.</p> |
