A controller (3) of a memory card is provided with a command decoding circuit (6) for decoding a command issued by a host (HT), a command enabling register (8) where validity/invalidity of the received command is set, and a command detection signal generating circuit (7) for detecting a valid command on the basis of the result of decoding by the command decoding circuit (6) and the set value of the command enabling register (8). When the command enabling register (8) receives a valid command, the command detection signal generating circuit (7) outputs a detection signal to a control unit (4) so as to execute a processing specific to each command. When the command enabling register (8) receives an invalid command, the command detection signal generating circuit (7) outputs no detection signal and ignores the command.
