Circuit arrangement for generating non-overlapping clock phases has first and second circuit units for combining two input signals, multiplexer unit receiving outputs of two units clock signal

摘要

The circuit arrangement has first and second circuit units (SE1,SE2) for combining two input signals to output signals, whereby a clock signal is fed to the first input of each unit, and a multiplexer unit (ME1) receiving the outputs of the two units and feeding their other inputs. A third input of the multiplexer unit for switching between the inputs of the unit receives a clock signal.