| 摘要 |
Error detection mechanisms for signal interfaces are disclosed, including built-in self-test (BIST) mechanisms (300) for testing multilevel signal interfaces (330). The error detection mechanisms may be provided in an integrated circuit (IC) chip that contains at least one of the signal interfaces or may be coupled to the interfaces on a printed circuit board (PCB). BIST mechanisms may include, for example, test signal generators (355, 362) and mechanisms (360) for determining whether the test signals generated are accurately transmitted and received by the interface. The BIST mechanisms may check a single input/output interface (330, 502), a group of interfaces (410, 420, 430) or may operate with a master device that tests a plurality of interfaces (616, 617). The error detection mechanisms may be particularly advantageous for testing memory circuits (611, 612, 613) designed to communicate according to multi-PAM signals over printed circuit boards (601).
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