发明名称 Phase locked loop for reducing electromagnetic interference
摘要 A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.
申请公布号 US2003058053(A1) 申请公布日期 2003.03.27
申请号 US20020253072 申请日期 2002.09.24
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JEON PHIL-JAE;LEE MYOUNG-SU
分类号 H03L7/08;H03C3/09;H03L7/099;H03L7/18;(IPC1-7):H03L7/00 主分类号 H03L7/08
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