发明名称 |
Issue and retirement mechanism in processor having different pipeline lenghths |
摘要 |
A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order. |
申请公布号 |
US2003061465(A1) |
申请公布日期 |
2003.03.27 |
申请号 |
US20020066984 |
申请日期 |
2002.02.04 |
申请人 |
YEH TSE-YU;KRUCKEMYER DAVID A.;ROGENMOSER ROBERT |
发明人 |
YEH TSE-YU;KRUCKEMYER DAVID A.;ROGENMOSER ROBERT |
分类号 |
G06F9/30;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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