发明名称 Method and apparatus for realigning bits on a parallel bus
摘要 An integrated circuit includes an alignment circuit. The alignment circuit includes a plurality of shift registers that are configured based on training bits transmitted to the integrated circuit via a parallel bus. After the shift registers are configured, the alignment circuit automatically aligns the data bits transmitted to the integrated circuit when the data bits are misaligned by one or more bit time intervals during transmission on the parallel bus.
申请公布号 US2003061527(A1) 申请公布日期 2003.03.27
申请号 US20010964010 申请日期 2001.09.26
申请人 INTEL CORPORATION 发明人 HAYCOCK MATTHEW B.;CASPER BRYAN K.
分类号 G06F1/04;(IPC1-7):G06F1/04 主分类号 G06F1/04
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