PROCESSOR SYSTEM HAVING JAVA ACCELERATOR

摘要

A processor system comprises a processor including an instruction decoder (22), a general−purpose register (61) having a plurality of register regions, and at least one functional unit (60) and a Java accelerator (30) for translating a Java byte code sequence into an instruction sequence intrinsic to the processor and feed the instruction sequence to the instruction decoder. The Java accelerator (30) includes a byte code translator (40) for translating the Java byte code sequence to an instruction sequence intrinsic to the processor and a register status control unit (50) for mapping a Java operand stack to a register region of the general−purpose register and for detecting a byte code, if any, which is redundant for the processor. When a redundant byte code is detected by the register status control unit (50), the feed of the intrinsic instruction from the byte code translator (40) to the instruction decoder (22) is suppressed.