发明名称 Method and apparatus for memory access scheduling to reduce memory access latency
摘要 A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.
申请公布号 US2003061459(A1) 申请公布日期 2003.03.27
申请号 US20010966957 申请日期 2001.09.27
申请人 ABOULENEIN NAGI;OSBORNE RANDY B.;HUGGAHALLI RAM;MADAVARAPU VAMSEE K.;CROCKER KEN M. 发明人 ABOULENEIN NAGI;OSBORNE RANDY B.;HUGGAHALLI RAM;MADAVARAPU VAMSEE K.;CROCKER KEN M.
分类号 G06F12/02;G06F13/16;(IPC1-7):G06F12/00 主分类号 G06F12/02
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