| 摘要 |
PURPOSE: A synchronous semiconductor memory device is provided to take in a row address and simultaneously start not only the operation of peripheral circuits but also the operation of the memory core. CONSTITUTION: A synchronous semiconductor memory device includes a bank timer(11) provided with a plurality of inverters(12a-12g), a NAND gate(13), a transfer gate(14), and a plurality of stages of delay sections(21a-21f). Each of the delay sections(21a-21f) is composed of a clocked inverter(22) controlled by signals(CKTRCNT, bCKTRCNT), a clocked inverter(23) controlled by signals(bCKTRCNT, CKTRCNT) and a NAND gate(24). Specifically, the bank active signal(BNKb) from the bank active controller is supplied to the input terminal of the inverter(12a). The output terminal of the inverter(12a) is connected to the input terminal of the inverter(12b). The output terminal of the inverter(12b) is connected to the input terminal of the inverter(12c) and one input terminal of the NAND gate(13). The output terminal of the inverter(12d) is connected to the other input terminal of the NAND gate(13).
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