Method and structure for stacked DRAM capacitors and FETs for embedded DRAM circuits

摘要

A method for fabricating stacked DRAM capacitors and FET structures for embedded circuits is achieved. The polysilicon capacitor bottom electrodes are formed first on the substrate in the memory regions. A single thin dielectric layer is formed over the bottom electrodes to serve as the interelectrode layer and concurrently on the device areas in the logic regions for the FET gate oxide. A second polysilicon layer is deposited and patterned to form the capacitor top electrodes and concurrently to form the FET gate electrodes. Next the lightly doped drains and source/drain contact areas are implanted to form FETs. Since the source/drain areas are formed after the DRAM capacitors are completed, the high-temperature thermal cycles for the DRAM capacitors are avoided. Therefore the FETs having shallow diffused junctions are formed without thermal degradation. The method also uses fewer processing steps to achieve these novel merged DRAM structures.