发明名称 |
Method for reducing the width of a global data bus in a memory architecture |
摘要 |
A memory architecture uses shared sense amplifiers (18-23) and a centralized cache (26-29) that contains M bits. The memory architecture also includes a global bus (31) connecting the sense amplifiers and the centralized cache. The global bus includes n bits, and n<M bits are transferred in M/n cycles to the centralized cache.
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申请公布号 |
US6538928(B1) |
申请公布日期 |
2003.03.25 |
申请号 |
US20000689219 |
申请日期 |
2000.10.11 |
申请人 |
ENHANCED MEMORY SYSTEMS INC. |
发明人 |
MOBLEY KENNETH J. |
分类号 |
G06F12/08;G11C7/10;G11C11/4091;G11C11/4093;(IPC1-7):G11C16/04 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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