发明名称 |
Semiconductor device and a method of fabricating the same |
摘要 |
The invention relates to a power MOSFET and reduction of the number of mask steps in a process of fabricating the power MOSFET. The increase of a parasitic capacitance due to the reduction is suppressed. In place of a thick insulating film 3, a gate insulating film 12 is formed on the entire surface of a semiconductor substrate. The gate-drain parasitic capacitance which uses the gate insulating film as a dielectric is suppressed by forming a removal region EL.
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申请公布号 |
US6537899(B2) |
申请公布日期 |
2003.03.25 |
申请号 |
US19980153346 |
申请日期 |
1998.09.15 |
申请人 |
SANYO ELECTRIC CO., LTD. |
发明人 |
KUBO HIROTOSHI;KUWAKO EIICHIROH |
分类号 |
H01L21/22;H01L21/336;H01L29/423;H01L29/78;H01L31/062;H01L31/113;H01L31/119;(IPC1-7):H01L21/22 |
主分类号 |
H01L21/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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