发明名称 |
Phase-locked loop circuit |
摘要 |
A phase locked loop wherein the voltage controlled oscillator is controlled by the output of a phase comparison circuit through a split loop filter. The oscillator has two varactors in parallel in its tuning circuit. The first branch of the loop filter includes an integrator filter generating a first error voltage and the second branch includes a low pass filter generating a second error voltage. The first error voltage controls one varactor and the second error voltage controls the other varactor. As a result the error voltages are effectively summed in the capacitance domain to obviate the need for a dedicated error voltage adder and to allow the total capacitance required in the loop filter to be reduced while still retaining an adequate signal to noise ratio in the filter.
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申请公布号 |
US6538519(B2) |
申请公布日期 |
2003.03.25 |
申请号 |
US20010977073 |
申请日期 |
2001.10.12 |
申请人 |
THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY |
发明人 |
LO CHI WA;LUONG HOWARD CAM |
分类号 |
H03L7/089;H03L7/099;(IPC1-7):H03L7/085;H03B5/00 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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