MEMORY CONTROL DEVICE AND SERIAL MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a memory control device and a serial memory prevented from malfunction by noise, allowing miniaturizing of the device, reducing of electric power consumption, and capable of treating a variable length command with simple constitution, and superior extendability. SOLUTION: A start bit S is detected by a start bit detecting circuit 20, and when a start bit detecting signal STB becomes a high level, a mask of an operation clock SK by an AND circuit 25 is released, and supply of a clock CK to a shift register 23 is started. The shift register 23 successively stores serial data DI according to the clock CK, and when the stored start bit S reaches the uppermost bit of the shift register 23, output of the AND circuit 25 is masked by an OR circuit 26, and the supply of the clock CK to the shift register 23 is checked. That is, the supply of the clock CK to the shift register 23 is performed only when storing data.