Multi-port memory device for a bus component has additional memory access paths that incorporate buffer memories in order to shorten wait states when the memory is already been accessed by another component

摘要

Memory device (4) for a component connected to a data bus comprises a memory (8) with a direct memory access path (6) and an additional memory access path (7, 9, 11; 7, 10, 12) for accessing at least one functional unit of the memory. The additional memory path comprises a buffer or cache memory (9, 10) and a DMA channel (11, 12). The invention also relates to a corresponding method for operation of a memory device whereby in a memory read access via the additional memory path the data in memory is first transferred to the buffer memory and then read from the buffer memory. In write memory access the data is first transferred to the buffer memory and then transferred to the main memory.