Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance

摘要

Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain regions a bitline stud layer separated from and rising above the storage capacitor. Within the memory cell structure, and at a minimum storage capacitor to bitline stud layer separation, a capacitor plate layer is further separated from the bitline stud layer than a capacitor node layer.