| 摘要 |
One embodiment of the present invention provides a system that facilitates inter-processor communication and synchronization through a hardware message buffer, which includes a plurality of physical channels that are structured as queues for communicating between processors in a multiprocessor system. The system operates by receiving an instruction to perform a data transfer operation through the hardware message buffer, wherein the instruction specifies a virtual channel to which the data transfer operation is directed. Next, the system translates the virtual channel into a physical channel, and then performs the data transfer operation on the physical channel within the hardware message buffer. In one embodiment of the present invention, if the data transfer operation is a store operation and the physical channel is already full, the system returns status information indicating that the physical channel is too full to perform the store operation. In one embodiment of the present invention, if the data transfer operation is a load operation and the physical channel is empty, the system returns status information indicating that the physical channel is empty and the load operation cannot be completed.
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