摘要 |
<p>PROBLEM TO BE SOLVED: To provide a delay circuit capable of outputting a delayed clock signal obtained by delaying a reference clock signal only for a desired delay quantity. SOLUTION: This delay circuit 10 is provided with a delaying part 11 where a plurality of delay elements D1 to DN for delaying an input signal are interconnected in series and the reference clock signal BCK is inputted to the delay element D1 of an input stage, a phase deciding part 12 for deciding the delay element for outputting the output signal with 360 deg. phase obtained by delaying the reference clock signal BCK only for an integer-multiple on the basis of output signals S1 to SN of the plurality of delay elements D1 to DN and the reference clock signal BCK, and a selecting part 13 for calculating a delay element for outputting the output signal obtained by delaying the reference clock signal BCK only for a desired delay quantity on the basis of results of this decision and outputting the output signal from the calculated delay element as a delayed clock signal DCK to the outside.</p> |