| 摘要 |
PROBLEM TO BE SOLVED: To provide a DTMIS FET which has small occupation area and is suitable for the formation of a logic gate. SOLUTION: This semiconductor integrated circuit has a gate electrode having a cross-shaped plane pattern having a longitudinal-axis electrode and a lateral-axis electrode crossing the longitudinal-axis electrode in its center, a 1st transistor having a n-well and p<+> type sources/drains formed in pair at both sides of an upper longitudinal axis above almost the center of the gate electrode, with the upper longitudinal axis between; and a 2nd transistor having a p-well and n<+> type sources/drains formed in a pair at both sides of a lower longitudinal axis below almost the center of the gate electrode, with the lower longitudinal axis between. Further, in a lateral axis electrode of the gate electrode, a 1st contact part which is a connecting part of the n-well and the gate electrode and a 2nd contact part of the p-well and the gate electrode are provided in a pair at the right and left of the longitudinal axis electrode of the gate electrode.
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