发明名称 |
Shared memory array |
摘要 |
Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.
|
申请公布号 |
US2003056075(A1) |
申请公布日期 |
2003.03.20 |
申请号 |
US20010953751 |
申请日期 |
2001.09.14 |
申请人 |
SCHMISSEUR MARK A.;MCCOSKEY JEFF;JEHL TIMOTHY J. |
发明人 |
SCHMISSEUR MARK A.;MCCOSKEY JEFF;JEHL TIMOTHY J. |
分类号 |
G06F12/08;G06F15/78;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|