| 摘要 |
PROBLEM TO BE SOLVED: To provide the simulation method and system of a semiconductor integrated circuit capable of precisely executing the back annotation of parasitic RC components extracted from layout design data when a degenerate state exists between a net list posterior to logical design and a net list posterior to layout design. SOLUTION: This system is constituted of a layout designing part 2 for generating a layout net list 3, a logic verifying part 4 for generating degeneration information by logically collating the net list 1 to the layout net list 3, an LPE extracting part 5 for generating an LPE extraction result file 6 and layout parasitic RC components, a net list generating part 8 for generating a net list 9 for simulation by using the degeneration information, the layout parasitic RC components, and LPE extraction result file 6, and a post layout simulation part 10 for executing post layout simulation by using the net list 9.
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