发明名称 CPU powerdown method and apparatus therefor
摘要 A CPU has a powerdown mode in which most of the circuitry does not receive power. Power-up, coming out of powerdown, is achieved in response to receiving an exception. Because most of the state information that is present in the CPU is not needed in response to an exception, there is no problem in removing power to most of the CPU during powerdown. The programmer's model register file and a few other circuits in the CPU are maintained in powerdown, but the vast majority of the circuits that make up the CPU: the execution unit, the instruction decode and control logic, instruction pipeline and bus interface, do not need to receive power. Removing power from these non-critical circuits results in significant power savings during powerdown. The powered circuits are provided with a reduced power supply voltage to provide additional power savings.
申请公布号 US2003056127(A1) 申请公布日期 2003.03.20
申请号 US20010956300 申请日期 2001.09.19
申请人 VAGLICA JOHN 发明人 VAGLICA JOHN
分类号 G06F1/04;G06F1/26;G06F1/32;G06F15/78;(IPC1-7):G06F1/26 主分类号 G06F1/04
代理机构 代理人
主权项
地址