CMOS sequential logic configuration for an edge triggered flip-flop

摘要

A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.