发明名称 |
Dual capacitor dynamic random access memory cell |
摘要 |
This invention discloses a dynamic random access memory (DRAM) memory cell. The DRAM memory cell includes a first transistor-capacitor circuit connected to a first bitline BL and a second transistor-capacitor circuit connected to a second bitline BL#. The memory cell further includes a gate of the first transistor connected to a gate of the second transistor. The DRAM cell further includes a sense amplifier connected to the first bit line BL and the second bit line BL# for measuring a binary bit from sensing a voltage difference between the first and second transistor-capacitor circuits independent from a pre-charged bit-line voltage.
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申请公布号 |
US2003053330(A1) |
申请公布日期 |
2003.03.20 |
申请号 |
US20020167383 |
申请日期 |
2002.06.10 |
申请人 |
UNIRAM TECHNOLOGY, INC. |
发明人 |
SHAU JENG-JYE;NA BYEONG-CHEAL |
分类号 |
G11C11/405;(IPC1-7):G11C11/24 |
主分类号 |
G11C11/405 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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