CAD TOOL FOR FAILURE ANALYSIS OF SEMICONDUCTOR AND FAILURE ANALYSIS METHOD OF SEMICONDUCTOR

摘要

PROBLEM TO BE SOLVED: To precisely execute a fault defining process of semiconductor in a short time in a CAD tool for presuming a defect and a failure analysis method using the CAD tool, by collating abnormal reaction information obtained by light emission analysis and OBIRCH analysis and layout data. SOLUTION: Information of plurality of abnormal reactions obtained by physically analyzing a semiconductor device is collected. Overlapping portions of the information are extracted and collated with the layout data on CAD. Wiring and defect portions each having the possibility of fault which are obtained by the collation on the layout data are converged.