Bus signal hold cell, bus system, and method

摘要

The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for holding the last state of the bus line. The outputs of the inverters are coupled with each other's inputs, respectively. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. An additional input is provided via which the bus signal hold cell can be charged with a defined test signal. The invention also relates to an integrated bus system and a method for driving a bus signal hold cell and a bus system.