<p>Methods and apparatus relating to a tightly coupled scalar and Boolean processor are described. In an embodiment, a Boolean unit may include a result vector subunit. The result vector subunit may be controlled by an instruction flow that is managed by a scalar unit. Other embodiments are also disclosed.</p>
申请公布号
EP1090485(A4)
申请公布日期
2003.03.19
申请号
EP19990928599
申请日期
1999.06.10
申请人
INTEL CORPORATION
发明人
NARAD, CHARLES, E.;FALL, KEVIN;MACAVOY, NEIL;SHANKAR, PRADIP;RAND, LEONARD, M.;HALL, JERRY, J.
