| 摘要 |
PURPOSE: A circuit for controlling ST(Serial Telecommunication) bus timing of an IS-95C(Interim Standard-95C) base station is provided to operate one high-speed global counter after multiplying a system clock, and to supply mutually different clocks and frame pulses meeting a requirement of an ST bus stream matching each device, so as to correctly adjust bus timing. CONSTITUTION: A clock multiplier(21) receives and multiplies system clocks. A high-speed global counter(22) generates mutually different clocks and frame pulses required in devices of a base station, such as a framer(23), a DSP(Digital Signal Processor)(24), and a switch(25) with one counter using the clocks multiplied by the clock multiplier(21). The clock multiplier(21) multiplies a system clock generated internally by the base station appropriately for a maximum clock among clocks used in the base station. And the high-speed global counter(22) performs count using the clock multiplied to the maximum clock used in the base station, thereby generating and providing the mutually different clocks and frame pulses required in each device of the base station.
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