| 摘要 |
An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)xfref, for a natural number M and reference clock signal frequency fref. The apparatus and associated method can flexibly produce a large variety of output clock frequencies and frequency ratios, lock to fref with a dynamic response independent of the output frequency range and can be optimized to a single reference frequency, need not relock to change output frequency, and reduce clock skew.
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