| 发明名称 |
Drain bias for non-volatile memory |
| 摘要 |
An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.
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| 申请公布号 |
US6535423(B2) |
申请公布日期 |
2003.03.18 |
| 申请号 |
US20000752370 |
申请日期 |
2000.12.29 |
| 申请人 |
INTEL CORPORATION |
发明人 |
TRIVEDI RITESH;BALTAR ROBERT;BAUER MARK;GULIANI SANDEEP;SRINIVASAN BALAJI |
| 分类号 |
G11C16/24;G11C16/28;(IPC1-7):G11C7/00 |
主分类号 |
G11C16/24 |
| 代理机构 |
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