Semiconductor storage device

摘要

An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.