Clock signal selection system, method of generating a clock signal and programmable clock manager including same

摘要

For use with a programmable clock manager (PCM), a selection system and method of generating a clock signal. In one embodiment, the selection system includes a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to an input signal with a fixed phase shift therebetween. The phase selector is further configured to select at least two of the phase shifted signals. The selection system further includes a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.