发明名称 |
Low power circuit with proper slew rate by automatic adjustment of bias current |
摘要 |
An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.
|
申请公布号 |
US6535039(B2) |
申请公布日期 |
2003.03.18 |
申请号 |
US20010921578 |
申请日期 |
2001.08.06 |
申请人 |
FUJITSU LIMITED |
发明人 |
NANBA HIROMI;MIZUTANI TOHRU;IKESHITA MAKOTO;TAKEYABU MASATO |
分类号 |
H03K5/12;G05F1/10;G11C27/02;H03F1/30;H03K5/24;H03K19/003;(IPC1-7):H03K5/12 |
主分类号 |
H03K5/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|