Method for generating behavior model description of circuit and apparatus for logic verification

摘要

A method for automatically generating a behavior model description of a circuit that is used with a simulator and a logic verification apparatus. An interface description defining the state transition of input/output signals of a logic circuit module at clock cycle accuracy and a functional description defining the processing function of signals or data of the logic circuit module as a program function are read, and a logic behavior model description of a circuit defining in-circuit behavior and a state transition of input/output signal at clock cycle accuracy is automatically generated.