发明名称 Synchronous counter
摘要 A synchronous counter includes at least three or more flip-flops having a chain structure, and at least two or more 2-input EXOR gates interposed in the chain structure. The number of stages of gates interposed between the output of one among the flip-flops and the input of another is one stage of a 2-input EXOR gate even in a critical path thereby shortening the critical path.
申请公布号 US6535569(B2) 申请公布日期 2003.03.18
申请号 US20010756129 申请日期 2001.01.09
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 NAKAJIMA MASAMI;KONDO HIROYUKI
分类号 H03K23/42;H03K23/54;(IPC1-7):H03K23/54 主分类号 H03K23/42
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