Logic gate circuit with low sub-threshold leakage current

摘要

The present invention relates to a logic gate circuit capable of reducing sub-threshold leakage current by applying the reverse voltage to the gate of a turned-off MOS device. The logic gate circuit in accordance with the present invention includes a CMOS logic gate having PMOS devices and NMOS devices with a low threshold voltage, a first voltage generator applying a first reverse voltage to the PMOS device of the CMOS logic gate during a pull-down operation, and a second voltage generator outputting a second reverse voltage to the NMOS device of the CMOS logic gate during a pull-up operation. The first voltage generator outputs a voltage greater than the source voltage by the threshold voltage to the first MOS device when the second MOS device performs a pull-down operation, and the second voltage generator outputs a voltage smaller than the earth voltage by the threshold voltage when the first MOS device performs a pull-up operation.